The invention relates to a process for synchronizing apparatuses connected to a communication network comprising wireless links. It applies in particular within the context of a domestic communication network. The invention also relates to apparatuses for implementing this process.
In an IEEE 1394 type bus described in the IEEE 1394-1995 standard, each apparatus (“node”) linked to the bus stamps the isochronous packets which it transmits with a time cue indicating the instant at which the packet is to be retrieved by the receiver apparatus.
Each apparatus (or “node”) linked to the bus comprises a 32-bit clock register incremented at the clock frequency of the bus, namely 24.576 MHz. This register (referred to as the “Cycle Time Register” in the IEEE 1394-1995 standard) is divided into three areas (the 12 lowest-order bits, the 13 intermediate-order bits and the 7 highest-order bits), which are therefore incremented at frequencies of 24.576 MHz, 8 KHz and 1 Hz respectively.
In the presence of apparatuses able to participate in isochronous traffic, and in order to synchronize these apparatuses, one of them is elected “Cycle master apparatus or node” (to use the IEEE 1394 terminology). The cycle master apparatus generates an isochronous frame or cycle start packet every 125 μs, this corresponding to a frequency of 8 KHz. This packet comprises the value of the 32-bits clock register of the cycle master apparatus at the moment of transmission. A packet receiver apparatus slaves its own 32-bit register to the values received from the cycle master apparatus.
The IEEE 1394-1995 document mentioned hereinabove relates to the architecture of the serial bus. An additional standard, relating to the interconnecting of several buses by way of bridges is currently being compiled. The latest version of this draft currently available from the IEEE has the reference P1394.1 draft 0.04, and dates from 7 Feb. 1999, the previous version dating from 18 Oct. 1997.
When several buses are interconnected by means of a bridge, it is vital to employ the same clock on either side of the bridge, for correct interpretation of the time markers of the packets and correction of clock drift.